FPGALab is an interactive virtual FPGA laboratory for Verilo...

Renaud Lifchitz

npub1renaud65zug8r570ndztde2xhk206z3v50a5mwa3kp2xshy3zmjqkqaw97

hex

55571b9ff4487f10740567c5e7492f014624474639872d26093c7e27529af787

nevent

nevent1qqs924cmnl6yslcswszk0308fyhsz33ygarrnpedycyncl3822d00pcprpmhxue69uhhyetvv9ujuem4d36kwatvw5hx6mm9qgspue77xa2pwyr3608ek39ku4rtm98apgk2876dhwcmq4rgtjg3deqk8dm4r

Kind-1 (TextNote)

2026-09-06T07:38:00Z

FPGALab is an interactive virtual FPGA laboratory for Verilog designs https://github.com/lmcapacho/FPGALab

原始 JSON

{
  "kind": 1,
  "id": "55571b9ff4487f10740567c5e7492f014624474639872d26093c7e27529af787",
  "pubkey": "1e67de3754171071d3cf9b44b6e546bd94fd0a2ca3fb4dbbb1b054685c9116e4",
  "created_at": 1788680280,
  "tags": [],
  "content": "FPGALab is an interactive virtual FPGA laboratory for Verilog designs \nhttps://github.com/lmcapacho/FPGALab",
  "sig": "629d275e3d71c6fb64948a75141583033a436e9641438115240a2dd51f470cd23cef5e4874946b909cf3da8506e8ae73434e3cd6e30b30f2fad1529c8db0b93b"
}